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MICRF501
Name
A1
A0
N1
N0
M1
M0
RxFilt
Pa2
Pa1
Pa0
Gc
ByLNA
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
Description
frequency divider A1, 6 bits
frequency divider A0, 6 bits
frequency divider N1, 12 bits
frequency divider N0, 12 bits
frequency divider M1, 10 bits
frequency divider M0, 10 bits
1=external capacitor for filtering of Rx data signal
gain setting in power amplifier
pa2, pa1, pa0 = 0 : lowest output power
pa2, pa1, pa0 = 1 : highest output power
gain control in power amplifier buffer: 1=high gain
gain control in preamplifier in receiver: 1=high gain
1 = the LNA is bypassed
reference settings in lock detector
all 0 ’ s: highest reference
all 1 ’ s: lowest reference
Micrel
Cpmp1
Cpmp0
charge pump setting:
Cpmp1=0, Cpmp0=0 : ± 125 μ A
Cpmp1=0, Cpmp0=1 : ± 500 μ A
Cpmp1=1, Cpmp0=0 : controlled by LockDet (LD) LD=0: ± 500 μ A, LD=1: ± 125 μ A
Cpmp1=1, Cpmp0=1 : same as previous in Tx. In Rx the current is ± 500 μ A.
Fc1
Fc0
Active RC-filter settings
Fc1=0, Fc0=0 : 10kHz
Fc1=0, Fc0=1 : 30kHz
Fc1=1, Fc0=0 : 60kHz
Fc1=1, Fc0=1 : 200kHz
OutS2
I- and Q-channel
OutS2 OutS1
OutS0 IchOut
QchOut
OutS2
OutS1
OutS0
IchOut
QchOut
OutS1
output select
0
0
0
high Z
high Z
1
0
0
lim_qch
gm_qch
OutS0
0 0 1 sk_ich sk_qch
0 1 0 gm_ich gm_qch
0 1 1 lim_ich lim_qch
1 0 1 gm_ich
1 1 0 high Z
1 1 1 N_div
lim_ich
Dual LF
M_div
sk:_*:Sallen-Key-filter output, gm_*:gyrator filter output, lim_*:limiter output, *_div:frequency divider output
(for testing). 110 is for dual-loop filter applications, see Modulation Outside PLL, Dual-Loop Filters.
Mod1
Mod0
RT
Pu
Mod1 = 0, Mod0 = 0: FSK modulation can be applied to the VCO
Mod1 = 0, Mod0 = 1: FSK modulation can be applied to the VCO: crystal modulation
Mod1 = 1, Mod0 = 0: FSK modulation by switching between the two sets of dividers
Mod1 = 1, Mod0 = 1: FSK modulation by adding/subtracting 1 to divider A1: f deviation = f comparison
0 = receive mode 1 = transmit mode
1 = power up, 0 = power down (When Pu=1, power down is controlled by PuExt)
Table 2. Bit Description
March 2003
15
MICRF501
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